This application is based on and claims priority of Japanese Patent Application No. 2002-238027 filed on Aug. 19, 2002, the entire contents of which are incorporated herein by reference.
A) Field of the Invention
The present invention relates to a solid state image pickup device, and more particularly to a charge coupled device (CCD) type solid state image pickup device.
B) Description of the Related Art
Various types of solid state image pickup devices have been proposed. If a semiconductor substrate is used, photodiodes are mainly used as photoelectric conversion elements. Known methods of detecting electric charges accumulated in photodiodes are mainly a charge coupled device (CCD) type and a MOS type. The CCD type is suitable for detecting an instantaneous image simultaneity because charges of a plurality of pixels can be transferred simultaneously. The MOS type is suitable for low voltage drive.
As the number of pixels is increased in order to realize a high resolution, the size of a photoelectric conversion element becomes small so that the amount of charges capable of being accumulated in each element reduces. In order to obtain a sufficiently large output from the reduced charge amount, it is desired to increase the gain of an output amplifier.
FIG. 3A is a schematic plan view showing the structure of a CCD type solid state image pickup device. Photodiodes PD are disposed in a light reception area in a matrix configuration of rows and columns. Along each column of the photodiodes PD, a vertical charge transfer path VCCD is disposed. At one ends of the vertical charge transfer paths VCCD, a horizontal charge transfer path HCCD is disposed. To one end of the horizontal charge transfer path HCCD, a floating diffusion FD is coupled via an output gate OG. A light shielding film 12 of W or the like is disposed covering the vertical charge transfer paths VCCD and horizontal charge transfer path HCCD. The light shielding film 12 has openings 11 at the positions above photodiodes.
Charges accumulated in the photodiodes PD are read to the vertical charge transfer paths VCCD and vertically transferred in the vertical charge transfer paths VCCD, for example, by four-phase drive, toward the horizontal charge transfer path HCCD one row after another. Upon reception of charges of one row, the horizontal charge transfer path HCCD transfers the charges at high speed, for example, by two-phase drive H1 and H2, and supplies each signal charge via the output gate OG to the floating diffusion FD. The floating diffusion FD generates a voltage V=Q/C where C is the capacitance of the floating diffusion and Q is the amount of charge received. This voltage is applied to the gate of an output amplifier transistor which outputs an image signal.
FIG. 3B is a schematic diagram showing the structure of the vertical charge transfer path VCCD and horizontal charge transfer path HCCD. A channel region CH of, for example, an n-type, is formed in a semiconductor substrate. A gate insulating film GI is formed on the surface of the channel region CH. On the gate insulating film GI, transfer electrodes made of a first polysilicon layer P1 are formed at every second positions.
The surfaces of the first polysilicon transfer electrodes P1 are oxidized to form an insulating film I1. A second polysilicon layer is formed on the insulating layer I1 or GI and patterned to form second polysilicon transfer electrodes P2. In the horizontal charge transfer path HCCD, impurities are doped in a channel CH at every second electrode positions in order to form built-in potential wells and barriers.
The surfaces of the second polysilicon transfer electrodes P2 are also oxidized to form an insulating layer I2. A light shielding film 12 having a opening 11 at the position above each photodiode PD is formed above the polysilicon transfer electrodes, covering the vertical charge transfer paths VCCD and horizontal charge transfer path HCCD. Another insulating layer may be deposited on the insulating layer I2.
FIG. 3C is a schematic cross sectional view showing the region from the output end of the horizontal charge transfer path HCCD to the output amplifier.
In the horizontal charge transfer path HCCD, the first polysilicon transfer electrode P1 and one of its nearby second polysilicon transfer electrodes, P2, are connected in common and supplied with a drive signal H1 (H2). Adjacent to the final stage of the horizontal charge transfer path HCCD, in the example shown in FIG. 3C an output gate OG made of the second polysilicon layer is formed.
The floating diffusion FD includes a high impurity concentration n-type region 1 disposed for receiving charges from HCCD via the output gate OG, and the channel region CH surrounding the n-type region 1.
An output amplifier transistor is surrounded by a field oxide film 4, and a gate electrode 7 is formed traversing the channel region of the output amplifier transistor and extends near to the floating diffusion FD. An aluminum layer 3 electrically connects the gate electrode 7 and the high impurity concentration region 1 of the floating diffusion FD. The aluminum layer 3 is also used as the wiring lines for the charge transfer electrodes.
The gate electrode 7 is made of the same polysilicon layer as that of the polysilicon transfer electrodes and has generally the same thickness as that of the polysilicon transfer electrodes. Namely, d1≈d2≈d3 where d1 is a thickness of the gate electrode, d3 is a thickness of the first polysilicon transfer electrode P1 and d2 is a thickness of the second polysilicon transfer electrode P2. For example, the thickness of each polysilicon electrode is about 0.4 xcexcm, and the size of the gate electrode 7 is 0.4 xcexcm to 2 xcexcm wide and 2 xcexcm to 10 xcexcm long.
In order to apply a high voltage to the gate electrode of the output amplifier when a predetermined amount of charges are accumulated in the floating diffusion FD, it is desired to reduce a parasitic capacitance of the floating diffusion FD. The capacitance can be reduced by reducing the areas of the floating diffusion FD and gate electrode 7. However, the reduction of parasitic capacitance is on the verge of limit.
An object of this invention is to provide a CCD type solid state image pickup device having an output amplifier with small parasitic capacitance.
According to one aspect of the present invention, there is provided a CCD type solid state image pickup device, comprising: a semiconductor substrate; a number of photoelectric conversion elements formed in and on the semiconductor substrate in a matrix configuration of rows and columns; a plurality of VCCDs each having a vertical channel region formed in the semiconductor substrate along each column of the photoelectric conversion elements, and a first set of charge transfer electrodes formed above the vertical channel region; an HCCD having a horizontal channel region formed in the semiconductor substrate and coupled to one ends of the VCCDs, and a second set of charge transfer electrodes formed above the horizontal channel region; a floating diffusion formed in the semiconductor substrate and coupled to one end of the HCCD; and an output amplifier including a pair of source/drain regions and an input gate electrode traversing above a region between the pair of source/drain regions, the input gate electrode having a portion extending at least near to the floating diffusion, and the input gate electrode being thinner than the first and second sets of charge transfer electrodes.
As the gate of the output transistor is made thin, the parasitic capacitance can be reduced so that the gain of the output amplifier can be increased.